Speculative Multiprocessor Cache Line Actions Using Instruction History

A technique is described for reducing miss latency in coherent-cache sharedmemory parallel computers. Miss latency is reduced by speculatively invalidating and downgrading (copying an exclusively held line back to memory) cache lines at one processor that might be needed at another processor. A line becomes a candidate for speculative invalidation when another line last accessed by the same instruction is invalidated. A line becomes a candidate for speculative downgrading under corresponding conditions. The technique can be implemented by constructing linked lists of lines for recent memory access instructions. The amount of memory needed by an implementation is little more than 11% the size of the cache. No time need be added to cache hits. In execution-driven simulations of such systems running programs from the SPLASH 2 suite invalidations and downgrades are reduced by 50% or more.